(Answered): Use the information provided.* List all of the hex memory addresses that will hit in set2.* List all ...

• The memory is byte addressable. • Memory accesses are to 1-byte words (not to 4-byte words). • Addresses are 13 bits wide. • The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S=8). The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Line 1 Line 0 Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 09 1 86 30 3F 10 00 0 45 1 60 EO BC 4F 23 OB 37 38 1 00 EB 0 OB 0 06 0 32 1 12 08 7B AD C7 1 06 78 07 C5 05 1 40 67 C2 3B 71 l 1 OB DE 18 4B 6E 0 91 1 ?0 B7 26 2D FO 0 46 0 DE 1 12 CO 88 37 I I 18 IS The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 11 10 9 8 7 6 5 4 3 2. 1 0